1. Technical Field
The present invention relates generally to interfacing between various processing circuitry employing media access control; and, more particularly, it relates to interrupt driven interfacing between a media access controller and a process controller.
2. Related Art
Conventional media access controllers (MACs) do not provide for upgradability to new specifications as new functionality is provided therein. Under traditional methods integrated circuitry that employs a media access controller (MAC), when a new specification is released to accommodate different data in a new manner, the media access controller (MAC) and the interfacing between the media access controller (MAC) and other control circuitry of a system must be redesigned in light of the hardware modification that must be performed to accommodate the data in compliance with the new specification. This inherent requirement for re-design and fabrication of the circuitry that performs the interfacing between the media access controller (MAC) and the other control circuitry in the system is very costly in terms of time and money. Not only must the design be performed, that requires a large amount of time in terms of engineering and fabrication, but the new circuitry must be installed within the system to perform properly on the data using the newly prescribed specification. For embedded systems, this xe2x80x9cupgradingxe2x80x9d of the new hardware, to be able to accommodate the new specification, will often lead to a total replacement of the integrated circuitry that contains the media access controller (MAC). The hard wired configuration of such conventional systems that perform media access control does not lend itself to easy upgradability to new specification that control the proper handling of data interfacing between various circuitry within the system employing media access control. The messages that govern the manner in which the data is transmitted and handled between the various circuitry are often modified with the introduction of a new specification. For example, when new messages are used within the specification to control the transportation of data between the various circuitry, the inability of the conventional interfacing between a media access controller (MAC) and a process controller typically necessarily requires a re-design and re-fabrication of an entirely new system, not only a re-design and re-fabrication of the interface itself.
In addition, the interfacing between the media access controller (MAC), between either a newly designed media access controller (MAC) to accommodate the new specification and a control processor or between a traditional media access controller (MAC) and a control processor, is oftentimes performed using conventional methods of polling and recurrent status detection between the various circuitry within the system. That is to say, in order to transfer data in the properly prescribed format between various portions of the system, as defined by the current specification in the media access control community, the transfer is typically performed using conventional polling and status detection circuitry that continually determines the existence of data among the various circuitry within the system performing media access control. The conventional solution of performing interfacing between the various circuitry is inherently slow, in that, it is primarily polling driven and inherently requires a large amount of bandwidth, in that, the detection of the status and the existence of data to be transferred between the various circuitry and processors is performed on a clock by clock basis, or almost nearly on a clock by clock basis. The conventional solution is consumptive in terms of bandwidth and hardware.
The conventional method of interfacing between the media access controller (MAC) and other control processor circuitry within the system performs the interfacing in such a way that the data is not necessarily protected during its transport between the various devices within the system. For example, in the event that read and write commands are executed simultaneously, there is a possibility that the data contained within these commands may be corrupted or overwritten thereby resulting in a significantly reduced performance of the overall system. Such data losses are undesirable in terms not only of system performance but also of user friendliness.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
Various aspects of the present invention can be found in a cable modem system that interfaces at least two processors to transfer data between the at least two processors. The cable modem system includes a first processor, a second processor, a memory, a semaphore circuitry, and an interrupt control circuitry. All of these elements are communicatively coupled with a bus. The memory stores a specification within a portion of the memory, and that specification governs the transfer of the data between the first processor and the second processor. Depending of the specific application that is being performed, either the first processor or the second processor writes the data to another portion of the memory. The semaphore circuitry determines which of the first processor and the second processor is to write the data to the other portion of the memory, and the interrupt control circuitry notifies the other of either the first processor or the second processor to read the data from the other portion of the memory.
In certain embodiments of the invention, the memory is, at least in part, a flash memory and the specification is stored within the flash memory. The memory is, at least in part, a random access memory, the random access memory is partitioned into a number of buffers wherein each of the number of buffers having a size and a location. The size and the location of each of the number of buffers is adjustable to conform with the specification. If desired, the specification is loaded into the memory using an external and portable media such as a floppy disk or a CD ROM. In some embodiments of the invention, the first processor and the second processor are embedded within a single circuitry. In others, they are separated and connected via an external bus structure. The first processor is contained within a cable modem, and the second processor is contained within a peripheral device wherein each of the cable modem and the peripheral device are communicatively coupled via the bus. The first processor and the second processor are each operable to perform a number of different processes that are defined by the specification.
Other aspects of the present invention can be found in an interrupt driven interface that couples a programmable media access controller (MAC) and a control processor for data transfer between them. The interrupt driven interface contains a memory, an interrupt control circuitry, and a bus that communicatively coupled the memory, the interrupt control circuitry, the programmable media access controller (MAC), and the control processor. The memory stores the data, and the data is transferred to the memory by either the programmable media access controller or the control processor. The interrupt control circuitry notifies the other of the programmable media access controller or the control processor to read the data from the memory after the transfer of the data to the memory.
In certain embodiments of the invention, the data is transferred to the memory by one of the programmable media access controller and the control processor after either the programmable media access controller or the control processor acquires a semaphore. A specification is stored within the memory, and the specification is downloaded from an external network. The control processor contains a message processor, and the message processor is operable to interpret a number of messages that are defined within the specification. The memory is partitioned into a number of buffers, each of the buffers has a size and a location. That is adjustable to conform with the specification.
Other aspects of the present invention can be found in a method to interface a programmable media access controller and a control processor. The method includes requesting a semaphore, writing data into a memory, releasing the semaphore, issuing an interrupt, requesting another semaphore, reading the data from the memory, and releasing the other semaphore.
In certain embodiments of the invention, the method also includes processing the semaphore to determine whether to write the data to the memory. If desired, it is further determined whether the semaphore is granted during the requesting of the semaphore, and if it is not granted, the a wait period of time is passed before performing an additional request of the semaphore. The method is operable to interface multiple device including the programmable media access controller, the control processor, and an additional processor. The method is operable to be performed within a cable modem system.